Verilog - IEEE Standard 1364-1995

2008 Oct 18

Syntax P1 P2

Verilog

Created by Gateway Design Automation in 1983, acquired by Cadence Design Systems. Is case sensitive. Has file IO capabilities. The module is the basic unit of description, and can be one of the following styles:

Dataflow Style - Uses the continuous assignment, assign, where anytime the right of the asignment changes the left hand side changes after the specified delay; the order of the statements does not matter since they are a parallel expression.
Behavioral Style - uses procedural constructs: an initial statement executed at time 0 and executed once, an always statement executes in a loop. Only a register data type can be assigned in either of these two statements.
Structural Style
Any mix of above

A delay is specified in time units, e.g.

   assign #2 sum = a^b;

   assign sum = #2 a^b;

Absolute time is specifed as follows:

   assign #2 sum <= a^b;

   assign sum <= #2 a^b;

The arbitrary time units are related to physical time with the following compiler directive:

   `timescale 1ns / 100 ps

which means each time unit is 1ns with a precision of 100ps (0.1ns). Without the above compiler directive the simulator uses the default time unit specified by the IEEE std.

Dataflow Style Example

module decoder2x4 (a, b, wn, z);
  input a, b, en;
  output [0:3]z;
  wire abar, bbar;
  assign @1 abar = ~a;
  assign @2 z[0] = ~(abar & bbar &en);
  assign @2 z[1] = ~(abar & b &en);
  assign @2 z[2] = ~(a & bbar &en);
  assign @2 z[3] = ~(a & b &en);
endmodule

Behavioral Style Example

module fa_seq (a, b, cin, sum, cout);
  input a, b, cin;
  output sum. cout;
  reg t1, t2, t3;
  always
    assign @1 abar = ~a;
    assign @2 z[0] = ~(abar & bbar &en);
    assign @2 z[1] = ~(abar & b &en);
    assign @2 z[2] = ~(a & bbar &en);
    assign @2 z[3] = ~(a & b &en);
  end
endmodule

Programming Language Interface (PLI)

Allows access to a verilog module.

External Links

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