Verilog Compiler Directives

Last updated 2008 Sep 17.

A compiler directive remains in effect (possibly spanning multipel files) until a different compiler directive specifies otherwise.

lower case only
`define `undef
`ifdef `else `endif
`default_nettype
`include
`resetall
`timescale
`unconnected_drive `nounconnected_drive
`celldefine `endcelldefine

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