A: Besides the class notes and the brief tutorial, there are at least 2 books on verilog. Terman Library has at least one. The one that I like better is Digital Design and Synthesis with Verilog VHDL, by Sternheim, Singh, Madhavan, and Trivedi (ISBN 0-9627488-2-X) published by the Automata Publishing Company (phone: 408-255-0705). The book comes with software (~$100) or without (~$70).
This is a link to a short description of most verilog features.
Also in Sweet Hall, there is a large Verilog-XL manual. It is along the wall with all of the other manuals.
Q: What is Magellan/Navigator? Why would I want to use it?
A: Magellan is a tool (or set of tools) that makes using verilog a little easier. Primarily we use Magellan to view a verilog.dump file. The dump file is a record of every transistion that occurs during a verilog simulation.
One of the main advantages of using Magellan over just the $gr_waves/$gr_addwaves calls from verilog, is that you can pull up signals at will. You don't have to type in every signal that you want to view before hand.
Documentation for Magellan can be found in /usr/class/ee/ssi/magellan/DOC/. In that dir you can find the user's manual ( text or ps ). Sample verilog files can be found in /usr/class/ee/ssi/magellan/SAMPLES/. There is a sample verilog file that has Magellan system tasks in it.
Q: How can I access a sub-field of an array element?
A: You can't do it in one reference. Let's say you have an array of 8 bit values declared with:
reg [7:0] addr [0:7].
If you want to look at the first 2 bits of addr[3], you must first put the array element into a temporary variable, before you can look at a sub-field. Using addr[3][7:6] or some variation thereof will NOT work.
Q: How can I print out the waveforms display?
A: Use the system task:
If you do it in the code, make sure that the $ps_waves statement is issued sometime after some actual simulation has occured. If you do it right at the start of the simulation there will be no waveforms to print to file.
Q: How can I generate a verilog.dump file suitable for Magellan?
A: Include the code fragment
initialThis will cause a verilog.dump file to be created in the current directory. For long simulations the verilog.dump file can get very large.
begin
$dumpvars;
end
Q: How can I read a file into verilog?
A: The system task $readmemb (and also $readmemh) will read in a file. It takes 2 arguments, the file name and the memory structure name. It reads the file into the memory structure. Words are white space separated (space, tab, return, etc). The difference between $readmemb and $readmemh is that, memb reads in binary, and memh reads in hex.
Here's a sample code fragment:
reg [13:0] Prog[4095:0]; // program to execute
initial
begin
// Here, it would be a good idea to initialize the Prog array with
// all zeros or something, just incase the read in file is
// shorter than the array.
$readmemb("Program", Prog);
end
Q: How can I send something to an output file?
A: There are many system tasks that are used for outputting to a file. Basically you need to open the file for writing, before you can write to it. This is a little module that prints "Hello" to the output file foo.dat. The Verilog-XL manual in Sweet Hall has more extensive documentation on the various system calls (try page 20-14).
Q: How can I use verilog to generate IRSIM test vectors?
A: By using special verilog system tasks, you can generate an IRSIM .cmd file from a verilog run. Please take a look at the document on snooper modules that is here.
Q: When I run my verilog with the snooper module, I get a really ugly looking error. It looks something like:
A: You probably ran verilog without the -x option. The snooper module needs verilog to be called with the -x option. This is the same as using rsimverilog.
Q: When I run verilog with a snooper module, I get a bunch of warnings about not being able to compare z's with irsim. What is going on?
A: Whereas in verilog where you can see a signal at high-z, in IRSIM nodes at retain their old value when tri-stated. What is happenning is that snooper is sampling a node in verilog that is high-z. However, it can't compare that to the IRSIM run, since a high-z node will hold its old value.
This is probably occuring when you are looking at some sort of shared bus. A way to get rid of the warnings is to alter the snooper.v module to only make asserts of the bus when one of the tri-state driver enables is on.
Q: Is there a function in verilog to generate random numbers?
A: Yes. It is $random(seed). The seed is optional. The random number sequence for a given seed (or no seed) will always be the same.
Q: I am getting a warning that looks like:
A: This means that in hooking together your verilog modules you did something wrong. On one of your connections, the number of bits that your module expects on a certain port does not match the number of bits of the thing that you hooked it up to.