Verilog Hints:

1. Inferred Storage. To avoid having the compiler infer storage elements (flip-flops) for you you simply need to make sure that every possible case is defined in combinational logic. This means that for every if/else-if you must have a final else with no dependencies to catch other cases and that for every case you must have a default. Also, do not use the non-blocking (<=) assignment operator.
2. Combinational Logic. Remember to include any wire on the Right Hand Side (RHS) of any expression in an always block in the sensetivity list for that block. Otherwise it will not be examined to see if the logic needs to change and you will end up creating inferred flip-flops. (Think about this until you understand why because it is important.)
3. What you think you can do, but can't. The verilog syntax has a lot of very nice constructs such as * / % for and while which do NOT map into logic. This means that you can write legal verilog which will simulate as you expect it will NOT translate into hardware. If it seems too good to be true (i.e., automatic instatiation of single-cycle 32-bit multiplier) then it probably is. Feel free to ask.
4. Debugging. The simulator we are using will sometimes not let you view a wire deep in your design and you will have to manually bring it up to the top level to view it. Try VERY hard to design and test each component separately so you don't have to debug many levels down. Remember that if something gives you a syntax error and you have no idea why or if it just doesn't work that a very good way to figure out your error is to comment out code around that area until you find out what does make it work and then go backwards from there. If you're trying to simulate a ROM make sure you use a distributed RAM for the simulations. You should then switch to a standard Block RAM for your final ROM, but it won't simulate.
5. CoreGen The Xilinx CoreGen module allows you to create optimized multipliers, filter, ROMs, RAMs, and a whole lot more. You use it through a very simple wizard-like interface and then you instantiate your module in your design. However, if you don't understand what all the options in the wizard are, you will probably not end up using the component correctly, so please read the documentation and ask the teaching staff. (I.e., if you're not sure what 'registered outputs' are or why you might or might not want them you should ask instead of accepting the default value.)