Verilog Keywords

Last updated 2008 Sep 17.

lower case only
always and assign begin buf bufif0 bufif1

case casex casez cmos deassign default defparam disable

edge else end endcase endmodule endfunction

endprimitive endspecify endtable endtaask event

for force forever fork function highz0 highz1

if ifnone initial inout input integer join large

macromodule medium module nand negedge nmos nor not notif0 notif1

or output parameter pmos posedge primitive pull0 pull1 pullup pulldown

rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1

scalared small specify specparam strong0 strong1 supply0 supply1

vectored wait wand weak0 weak1 while wire wor xnor xor

© 2005-2008 Prem Sobel. All Rights Reserved.